This invention relates to analog to digital converters, and more particularly to a high precision analog to digital converter (ADC) compensating for capacitor mismatch errors in a switched capacitor ADC.
Analog to digital converters (ADCs) convert analog input signals into digital signals. Such ADCs are used in many applications such as video, audio, and signal sensing applications. One type of ADC is sigma-delta converter utilizing over-sampling techniques. Such an ADC generally includes an analog modulator portion and digital filtering and decimation portion. The analog modulator portion essentially digitizes an analog input signal at very high sampling rates, i.e., sampling rates greater than the Nyquist rate, in order to perform a noise shaping function. Then, the digital filtering portion allows the ADC to achieve a high resolution. Decimation is thereafter used to reduce the effective sampling rate back to the Nyquist rate.
It is known that the analog modulator portion may generally include a feed forward path including a summing circuit, a filter, and a single bit A/D converter. A feed back path may further include a single bit digital to analog converter (DAC) coupled to the output of the single bit A/D converter and the summation circuit to provide a negative feed back signal to the summation circuit. Besides accepting the feed back signal from the DAC, the summation circuit also accepts an input analog signal for conversion.
In a switched capacitor ADC having a pair of input terminals to accept an input analog signal, an input switch array including a pair of input capacitors coupled to associated input terminals may be provided. In addition, an integrator having a pair of integration capacitors may act as the filter. The integrator may be further coupled to a comparator which functions as the A/D converter.
Ideally, the pair of input capacitors is matched with each other and the pair of integration capacitors is matched with each other. However, some capacitor mismatch is generally inevitable resulting in mismatched gain and offset. This can cause unacceptable non-linearity and offset problems where a high precision ADC is required.
Accordingly, there is a need for an apparatus and method that overcomes the above deficiencies in the prior art to allow for ADC with improved precision performance in the presence of capacitor mismatching.
An ADC consistent with the invention includes: an input switch array having a first output and a first input and a first input capacitor coupled between the first input and the first output, the input switch array also has a second output and a second input and a second input capacitor coupled between the second input and the second output; an integrator having a first integrator output and a first integrator input and a first integrator capacitor coupled between the first integrator input and the first integrator output, the integrator also having a second integrator output and a second integrator input and a second integrator capacitor coupled between the second integrator input and the second integrator output; and a cross switch array coupled between the input switch array and the integrator configured to alternately transfer charges from the first input capacitor and the second input capacitor to the first integration capacitor and the second integration capacitor.
An ADC consistent with the invention may also include a cross switch array configured to transfer charges from the first input capacitor to the first integration capacitor and from the second input capacitor to the second integration capacitor during a first charge transfer time interval, and wherein the cross switch array is further configured to transfer charges from the first input capacitor to the second integration capacitor and from the second input capacitor to the first integration capacitor during a second charge transfer time interval.
In another embodiment, an ADC consistent with the invention may also include: an analog modulator configured to receive an analog input signal and output a sampled signal representative of the analog input signal; and a digital filter configured to receive the sampled signal and output a digital signal representative of the analog input signal, wherein the analog modulator includes: a feed forward path configured to accept the analog input signal and provide the sampled signal to the digital filter; and a feed back path having a digital to analog converter (DAC) configured to accept the sampled signal and convert the sampled signal to a feed back analog signal, wherein the DAC includes: a reference terminal configured to receive a reference signal; and a first conductive path coupled to the reference terminal and a first node, wherein the first conductive path includes a first reference capacitor and a plurality of switches, wherein the plurality of switches of the first conductive path are responsive to an associated plurality of control signals to create a positive reference signal at the first node during a first time interval and a negative reference signal at the first node during a second time interval.
An analog modulator for use in an analog to digital converter consistent with the invention includes: a pair of input capacitors including a first input capacitor and a second input capacitor; a pair of integration capacitors including a first integration capacitor and a second integration capacitor; and a cross switch array coupled between the pair of input capacitors and the pair of integration capacitors configured to cross couple the pair of input capacitors to the pair of integration capacitors during a charge transfer time interval.
A DAC consistent with the invention includes: a reference terminal configured to receive a reference signal; and a first conductive path coupled to the reference terminal and a first node, wherein the first conductive path includes a first reference capacitor and a plurality of switches, wherein the plurality of switches of the first conductive path are responsive to an associated plurality of control signals to create a positive reference signal at the first node during a first time interval and a negative reference signal at the first node during a second time interval.
In another embodiment, an ADC consistent with the invention includes: an integrator having an integrator input and an integrator output; a comparator having a comparator input coupled to the integrator output, wherein the comparator is configured to output digital data samples during a first comparison time interval and a second non-overlapping comparison time interval; and a feedback switching circuit configured to accept a reference source and the digital data samples and provide a feedback signal to the integrator, wherein noise from said reference source is dissipated by having a first charge transfer time interval and a second non-overlapping charge transfer time interval occurring after the first comparison time interval and before the second comparison time interval.
A sensing system consistent with the invention includes: a power source having a power characteristic; a sensor configured to sense the power characteristic and provide a first analog signal and a second analog signal representative of the power characteristic; and an ADC configured to accept the first and second analog signal and provide a digital signal representative of the first and second analog signal, wherein the ADC includes: an input switch array having a first output and a first input and a first input capacitor coupled between the first input and the first output, the input switch array also having a second output and a second input and a second input capacitor coupled between the second input and the second output, wherein the first input is configured to receive the first analog signal and the second input is configure to receive the second analog signal; an integrator having a first integrator output and a first integrator input and a first integrator capacitor coupled between the first integrator input and the first integrator output, the integrator also having a second integrator output and a second integrator input and a second integrator capacitor coupled between the second integrator input and the second integrator output; and a cross switch array coupled between the input switch array and the integrator configured to alternately transfer charges from the first input capacitor and the second input capacitor to the first integration capacitor and the second integration capacitor.
A method of transferring charges in an analog to digital converter from a first input capacitor and a second input capacitor to a first integration capacitor and a second integration capacitor consistent with the invention includes the steps of: transferring charges from the first input capacitor to the first integration capacitor and from the second input capacitor to the second integration capacitor during a first charge transfer time interval; and transferring charges from the first input capacitor to the second integration capacitor and from the second input capacitor to the first integration capacitor during a second charge transfer time interval.
A method of converting an input analog signal to digital output samples consistent with the invention includes the steps of: charging a first input capacitor and a second input capacitor by the input analog signal during a first and a third non-overlapping time interval; and transferring charges alternately from the first input capacitor and the second input capacitor to a first integration capacitor and a second integration capacitor during a second and a fourth non-overlapping time interval.
A method of sampling and transferring charges in an ADC consistent with the invention includes the steps of: providing a first analog signal to a first input terminal and a second analog signal to a second input terminal of the ADC; sampling the first analog signal at a first input capacitor during a first sampling time interval and the second analog signal at a second input capacitor during the first sampling time; transferring charges sampled by the first input capacitor to a first integration capacitor and charges sampled by the second input capacitor to a second integration capacitor during a first charge transfer time interval; sampling the second analog signal at said first input capacitor and the first analog signal at the second input capacitor during a second sampling time interval; and transferring charges sampled by the first input capacitor to the second integration capacitor and charges sampled by the second input capacitor to the first integration capacitor during a second charge transfer time interval.
Finally, a method of reducing the effects of noise from a reference signal source used in a DAC, where the DAC is coupled to a feedback path of an ADC, consistent with the invention includes the steps of: charging a first reference capacitor and a second reference capacitor of the DAC by the reference signal during a first and a third non-overlapping time interval; transferring charges alternately from the first reference capacitor and the second reference capacitor to a first integration capacitor and a second integration capacitor during a second and a fourth non-overlapping time interval; and comparing charges transferred with a reference charge in a fifth time interval, wherein the fourth time interval occurs after the second time interval, and the fifth time interval occurs after the fourth time interval.